The FrontPanel Subsystem Vivado IP Core is an HDL generator that handles the interconnection and instantiation
of the FrontPanel HDL components delivered within the FrontPanel SDK. The core embeds both the synthesis and
behavioral simulation cores into the same instantiation, allowing for rapid verification. IPI Block Designer
support allows for schematic style digital design development and embedded example designs demonstrate the various
features of the IP Core.

Getting Started, How-To Guides, Technical Reference, and Discussion documentation are located at: 
https://docs.opalkelly.com/fpsdk/frontpanel-hdl/vivado-ip-core/
